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authorEddie Hung <eddie@fpgeh.com>2020-03-17 10:22:33 -0700
committerEddie Hung <eddie@fpgeh.com>2020-03-17 10:22:33 -0700
commit8c45ea9f0e7ce111f56edc54d6acbd2417cce61f (patch)
treec2b9418d0b04891a149dd9657f48e460bfea1f78 /kernel/sigtools.h
parentbc51e609cbe00948cf0cae4d58ff36616ff85679 (diff)
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kernel: use const reference for SigSet too
Diffstat (limited to 'kernel/sigtools.h')
-rw-r--r--kernel/sigtools.h36
1 files changed, 18 insertions, 18 deletions
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 37674df81..10b39a89e 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -155,65 +155,65 @@ struct SigSet
void insert(const RTLIL::SigSpec &sig, T data)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
if (bit.wire != NULL)
bits[bit].insert(data);
}
- void insert(RTLIL::SigSpec sig, const std::set<T> &data)
+ void insert(const RTLIL::SigSpec& sig, const std::set<T> &data)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
if (bit.wire != NULL)
bits[bit].insert(data.begin(), data.end());
}
- void erase(RTLIL::SigSpec sig)
+ void erase(const RTLIL::SigSpec& sig)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
if (bit.wire != NULL)
bits[bit].clear();
}
- void erase(RTLIL::SigSpec sig, T data)
+ void erase(const RTLIL::SigSpec &sig, T data)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
if (bit.wire != NULL)
bits[bit].erase(data);
}
- void erase(RTLIL::SigSpec sig, const std::set<T> &data)
+ void erase(const RTLIL::SigSpec &sig, const std::set<T> &data)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
if (bit.wire != NULL)
bits[bit].erase(data.begin(), data.end());
}
- void find(RTLIL::SigSpec sig, std::set<T> &result)
+ void find(const RTLIL::SigSpec &sig, std::set<T> &result)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
if (bit.wire != NULL) {
auto &data = bits[bit];
result.insert(data.begin(), data.end());
}
}
- void find(RTLIL::SigSpec sig, pool<T> &result)
+ void find(const RTLIL::SigSpec &sig, pool<T> &result)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
if (bit.wire != NULL) {
auto &data = bits[bit];
result.insert(data.begin(), data.end());
}
}
- std::set<T> find(RTLIL::SigSpec sig)
+ std::set<T> find(const RTLIL::SigSpec &sig)
{
std::set<T> result;
find(sig, result);
return result;
}
- bool has(RTLIL::SigSpec sig)
+ bool has(const RTLIL::SigSpec &sig)
{
for (auto &bit : sig)
if (bit.wire != NULL && bits.count(bit))
@@ -289,14 +289,14 @@ struct SigMap
void add(const RTLIL::SigBit &bit)
{
- RTLIL::SigBit b = database.find(bit);
+ const auto &b = database.find(bit);
if (b.wire != nullptr)
database.promote(bit);
}
void add(const RTLIL::SigSpec &sig)
{
- for (auto &bit : sig)
+ for (const auto &bit : sig)
add(bit);
}
@@ -335,7 +335,7 @@ struct SigMap
RTLIL::SigSpec allbits() const
{
RTLIL::SigSpec sig;
- for (auto &bit : database)
+ for (const auto &bit : database)
if (bit.wire != nullptr)
sig.append(bit);
return sig;