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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-18 07:33:53 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-18 07:33:53 +0100 |
| commit | bc5489f7ec22628553c587df3bcf40cea47cf755 (patch) | |
| tree | 161eb60f3165149eef22ce57024338c022a3f9b7 /kernel/show.cc | |
| parent | ba3793b6420f2a0288c43be0cd4016fd5473acaf (diff) | |
| parent | 020a35d11e26e5487ae3568ac78df28c14019375 (diff) | |
| download | yosys-bc5489f7ec22628553c587df3bcf40cea47cf755.tar.gz yosys-bc5489f7ec22628553c587df3bcf40cea47cf755.tar.bz2 yosys-bc5489f7ec22628553c587df3bcf40cea47cf755.zip | |
Merge branch 'hansi'
Diffstat (limited to 'kernel/show.cc')
| -rw-r--r-- | kernel/show.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/show.cc b/kernel/show.cc index c556c9914..50cddce9b 100644 --- a/kernel/show.cc +++ b/kernel/show.cc @@ -319,7 +319,7 @@ struct ShowPass : public Pass { log(" Also run the specified command with the postscript file as parameter.\n"); log("\n"); log(" -lib <verilog_or_ilang_file>\n"); - log(" Use the specified library file for determining whether cell ports are.\n"); + log(" Use the specified library file for determining whether cell ports are\n"); log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); log("\n"); |