diff options
| author | Jannis Harder <me@jix.one> | 2022-07-21 14:22:15 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-08-16 13:37:30 +0200 |
| commit | c0063288d699f4f3edf5e0ff6ee1bd5cfa9ac884 (patch) | |
| tree | 56dede2b6f394bdd4cf662ae8f8a9c1f67e8f54f /kernel/satgen.cc | |
| parent | c26b2bf543a226e65a3fb07040bb278d668accf2 (diff) | |
| download | yosys-c0063288d699f4f3edf5e0ff6ee1bd5cfa9ac884.tar.gz yosys-c0063288d699f4f3edf5e0ff6ee1bd5cfa9ac884.tar.bz2 yosys-c0063288d699f4f3edf5e0ff6ee1bd5cfa9ac884.zip | |
Add the $anyinit cell and the formalff pass
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
Diffstat (limited to 'kernel/satgen.cc')
| -rw-r--r-- | kernel/satgen.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/satgen.cc b/kernel/satgen.cc index 9c40ec66d..05eeca76e 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -1176,7 +1176,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) return true; } - if (timestep > 0 && RTLIL::builtin_ff_cell_types().count(cell->type)) + if (timestep > 0 && (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit))) { FfData ff(nullptr, cell); |