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author | Clifford Wolf <clifford@clifford.at> | 2019-08-10 09:52:14 +0200 |
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committer | GitHub <noreply@github.com> | 2019-08-10 09:52:14 +0200 |
commit | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (patch) | |
tree | 21d24c49c50f17a53a9bc8fe4118752ff845e55d /kernel/rtlil.h | |
parent | 4f812131653ebea06e3d1c3e7599492992edb771 (diff) | |
parent | 6d77236f3845cd8785e7bdd4da3c5ef966be6043 (diff) | |
download | yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.gz yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.bz2 yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.zip |
Merge pull request #1258 from YosysHQ/eddie/cleanup
Cleanup a few barnacles across codebase
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r-- | kernel/rtlil.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c07d39c65..37b5f984c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -276,20 +276,24 @@ namespace RTLIL return std::string(c_str() + pos, len); } + int compare(size_t pos, size_t len, const char* s) const { + return strncmp(c_str()+pos, s, len); + } + bool begins_with(const char* prefix) const { size_t len = strlen(prefix); if (size() < len) return false; - return substr(0, len) == prefix; + return compare(0, len, prefix) == 0; } bool ends_with(const char* suffix) const { size_t len = strlen(suffix); if (size() < len) return false; - return substr(size()-len) == suffix; + return compare(size()-len, len, suffix) == 0; } size_t size() const { - return str().size(); + return strlen(c_str()); } bool empty() const { @@ -1404,7 +1408,7 @@ struct RTLIL::Process : public RTLIL::AttrObject inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { } inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } -inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { } +inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { } inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } |