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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
| commit | bdc316db50cd8b68ef096386a89c1b38793784e1 (patch) | |
| tree | 507341053afa28df1a753ef9de33c3d096683720 /kernel/rtlil.h | |
| parent | 2733994aeba0879533cc1a871aae84497b32ff9e (diff) | |
| download | yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.gz yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.bz2 yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.zip | |
Added $anyseq cell type
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 109e33351..9430dcb36 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1108,6 +1108,7 @@ public: RTLIL::SigBit Oai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d); RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1); + RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1); RTLIL::SigSpec Initstate (RTLIL::IdString name); }; |