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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-19 15:48:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-19 15:48:40 +0200 |
| commit | 9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68 (patch) | |
| tree | 74840e34ae02c49884e81916eb81be4fd93c006d /kernel/rtlil.h | |
| parent | ca91bccb6b03a0b098f80bf14b55a1444eef73c0 (diff) | |
| parent | a8200a773fb8cf2ce2d8793716b62e01c97dd731 (diff) | |
| download | yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.tar.gz yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.tar.bz2 yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.zip | |
Merge branch 'sv_packages' of https://github.com/rubund/yosys
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 940e36ab3..274f97023 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -792,6 +792,7 @@ struct RTLIL::Design int refcount_modules_; dict<RTLIL::IdString, RTLIL::Module*> modules_; + std::vector<AST::AstNode*> verilog_packages; std::vector<RTLIL::Selection> selection_stack; dict<RTLIL::IdString, RTLIL::Selection> selection_vars; |