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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-31 12:18:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-31 12:18:03 -0700 |
| commit | 84c7a562e597aaaacaab122a2ec7cbdf67ff6cfc (patch) | |
| tree | 0b9565b35d88a5e8627f87bd1001201206bdc0f4 /kernel/rtlil.h | |
| parent | 2f71c2c2198b05e216524feb94b66d14c9c433c0 (diff) | |
| download | yosys-84c7a562e597aaaacaab122a2ec7cbdf67ff6cfc.tar.gz yosys-84c7a562e597aaaacaab122a2ec7cbdf67ff6cfc.tar.bz2 yosys-84c7a562e597aaaacaab122a2ec7cbdf67ff6cfc.zip | |
Helper: SigSpec::operator[] to accept negative indices
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 868aaaa14..1ed055715 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -734,8 +734,8 @@ public: inline int size() const { return width_; } inline bool empty() const { return width_ == 0; } - inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); } - inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); } + inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return index >= 0 ? bits_.at(index) : bits_.at(width_ + index); } + inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return index >= 0 ? bits_.at(index) : bits_.at(width_ + index); } inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } |