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| author | Clifford Wolf <clifford@clifford.at> | 2017-08-18 11:45:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-18 11:45:15 +0200 |
| commit | 35760dd784f4b2e360a4137ce115104d1204d7a6 (patch) | |
| tree | c54e9ef38bb80d410420a1e5c2b1e4f5fca81072 /kernel/rtlil.h | |
| parent | 864498527a39716a59e7531cf55bc6b8b7a1f1ed (diff) | |
| parent | d30cc60ba9148346173a1ed26f0ce833de522003 (diff) | |
| download | yosys-35760dd784f4b2e360a4137ce115104d1204d7a6.tar.gz yosys-35760dd784f4b2e360a4137ce115104d1204d7a6.tar.bz2 yosys-35760dd784f4b2e360a4137ce115104d1204d7a6.zip | |
Merge branch 'sim'
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 51a3fad6f..be558932f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -479,6 +479,10 @@ struct RTLIL::Const inline RTLIL::State &operator[](int index) { return bits.at(index); } inline const RTLIL::State &operator[](int index) const { return bits.at(index); } + bool is_fully_zero() const; + bool is_fully_def() const; + bool is_fully_undef() const; + inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { RTLIL::Const ret; ret.bits.reserve(len); |