diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-08-24 15:14:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-24 15:14:00 +0200 |
| commit | eda603105e2aa72441bfc07662774a20f3b978fe (patch) | |
| tree | f345bb4cc553ab8c7f2ed7a61aad1dfc46a4e65f /kernel/rtlil.cc | |
| parent | 9c5a63c52c24f0570557b4bf7340b41666cf44b6 (diff) | |
| download | yosys-eda603105e2aa72441bfc07662774a20f3b978fe.tar.gz yosys-eda603105e2aa72441bfc07662774a20f3b978fe.tar.bz2 yosys-eda603105e2aa72441bfc07662774a20f3b978fe.zip | |
Added is_signed argument to SigSpec.as_int() and Const.as_int()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 28a451345..df4d8b092 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -92,12 +92,15 @@ bool RTLIL::Const::as_bool() const return false; } -int RTLIL::Const::as_int() const +int RTLIL::Const::as_int(bool is_signed) const { - int ret = 0; + int32_t ret = 0; for (size_t i = 0; i < bits.size() && i < 32; i++) if (bits[i] == RTLIL::S1) ret |= 1 << i; + if (is_signed && bits.back() == RTLIL::S1) + for (size_t i = bits.size(); i < 32; i++) + ret |= 1 << i; return ret; } @@ -2647,14 +2650,14 @@ bool RTLIL::SigSpec::as_bool() const return false; } -int RTLIL::SigSpec::as_int() const +int RTLIL::SigSpec::as_int(bool is_signed) const { cover("kernel.rtlil.sigspec.as_int"); pack(); log_assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) - return chunks_[0].data.as_int(); + return chunks_[0].data.as_int(is_signed); return 0; } |