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author | Clifford Wolf <clifford@clifford.at> | 2015-01-01 11:41:52 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-01-01 11:41:52 +0100 |
commit | e62d838bd424995d2fcdc9cef1f56752905c3b4d (patch) | |
tree | 1699bd05ec11dcf7cd38e1141eeeb58019008908 /kernel/rtlil.cc | |
parent | 327a5d42b6b396f1c210f1579d03a0806a261d84 (diff) | |
download | yosys-e62d838bd424995d2fcdc9cef1f56752905c3b4d.tar.gz yosys-e62d838bd424995d2fcdc9cef1f56752905c3b4d.tar.bz2 yosys-e62d838bd424995d2fcdc9cef1f56752905c3b4d.zip |
Removed SigSpec::extend_xx() api
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index cd2232c8c..d396d6c24 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2673,24 +2673,6 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) check(); } -void RTLIL::SigSpec::extend_xx(int width, bool is_signed) -{ - cover("kernel.rtlil.sigspec.extend_xx"); - - pack(); - - if (width_ > width) - remove(width, width_ - width); - - if (width_ < width) { - RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; - if (!is_signed && (padding == RTLIL::State::S1 || padding.wire)) - padding = RTLIL::State::S0; - while (width_ < width) - append(padding); - } -} - void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { cover("kernel.rtlil.sigspec.extend_u0"); |