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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-11-25 17:43:28 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-11-25 17:43:28 +0100 |
| commit | addc493e8d7f64267661af3bf7fbaf265e2b17ba (patch) | |
| tree | 6eb04bf55fea7f68af8fef8c7803d41ba31f3d9b /kernel/rtlil.cc | |
| parent | cf67e6a3977410e039d62a1e9f6c49c42cb97b08 (diff) | |
| download | yosys-addc493e8d7f64267661af3bf7fbaf265e2b17ba.tar.gz yosys-addc493e8d7f64267661af3bf7fbaf265e2b17ba.tar.bz2 yosys-addc493e8d7f64267661af3bf7fbaf265e2b17ba.zip | |
generate only simple assignments in verilog backend
Diffstat (limited to 'kernel/rtlil.cc')
0 files changed, 0 insertions, 0 deletions