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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-14 02:17:01 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-14 02:17:01 +0100 |
| commit | a48ec49017a8a792841cf486167c643db23eeb22 (patch) | |
| tree | e1ec8f80c4c000275ca7e1c219947ea234cf6bf9 /kernel/rtlil.cc | |
| parent | 546de7fa4fbd1b54e125fac06b588dbecfb033e0 (diff) | |
| parent | 590e6961cb2ff352c2c01d5fcf6307db95d37129 (diff) | |
| download | yosys-a48ec49017a8a792841cf486167c643db23eeb22.tar.gz yosys-a48ec49017a8a792841cf486167c643db23eeb22.tar.bz2 yosys-a48ec49017a8a792841cf486167c643db23eeb22.zip | |
Merge branch 'master' into btor-ng
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7dc7107c1..3e873054f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -172,6 +172,17 @@ bool RTLIL::Const::is_fully_zero() const return true; } +bool RTLIL::Const::is_fully_ones() const +{ + cover("kernel.rtlil.const.is_fully_ones"); + + for (auto bit : bits) + if (bit != RTLIL::State::S1) + return false; + + return true; +} + bool RTLIL::Const::is_fully_def() const { cover("kernel.rtlil.const.is_fully_def"); |