Merge branch 'xaig' into xc7mux

1 files changed, 3 insertions, 10 deletions

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f732b56b0..3990ec283 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1565,21 +1565,14 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 
 void RTLIL::Module::remove(RTLIL::Cell *cell)
 {
-	auto it = cells_.find(cell->name);
-	log_assert(it != cells_.end());
-	remove(it);
-}
-
-dict<RTLIL::IdString, RTLIL::Cell*>::iterator RTLIL::Module::remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it)
-{
-	RTLIL::Cell *cell = it->second;
 	while (!cell->connections_.empty())
 		cell->unsetPort(cell->connections_.begin()->first);
 
+	auto it = cells_.find(cell->name);
+	log_assert(it != cells_.end());
 	log_assert(refcount_cells_ == 0);
-	it = cells_.erase(it);
+	cells_.erase(it);
 	delete cell;
-	return it;
 }
 
 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)