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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-30 18:59:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-30 18:59:05 +0200 |
| commit | 4724d94fbce587b39cd7343dc8de3b859311f55c (patch) | |
| tree | 6a1c2a9b82d48f73dbcaa3926003bbcf85b48a0f /kernel/rtlil.cc | |
| parent | 88db09255baa92facbe2736937ef113dc1503e9b (diff) | |
| download | yosys-4724d94fbce587b39cd7343dc8de3b859311f55c.tar.gz yosys-4724d94fbce587b39cd7343dc8de3b859311f55c.tar.bz2 yosys-4724d94fbce587b39cd7343dc8de3b859311f55c.zip | |
Added $alu cell type
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7ba6911a2..96b651d89 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -557,6 +557,20 @@ namespace { return; } + if (cell->type == "$alu") { + param_bool("\\A_SIGNED"); + param_bool("\\B_SIGNED"); + port("\\A", param("\\A_WIDTH")); + port("\\B", param("\\B_WIDTH")); + port("\\CI", 1); + port("\\BI", 1); + port("\\X", param("\\Y_WIDTH")); + port("\\Y", param("\\Y_WIDTH")); + port("\\CO", param("\\Y_WIDTH")); + check_expected(); + return; + } + if (cell->type == "$logic_not") { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); |