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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
| commit | 369bf81a7049c96f62af084bb5007fbf45e36ab4 (patch) | |
| tree | 92071580c9bd60888ee5861d59457947a8adfde7 /kernel/rtlil.cc | |
| parent | ecc30255ba70910777a4586f5bd6abc818073293 (diff) | |
| download | yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.gz yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.bz2 yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.zip | |
Added support for non-const === and !== (for miter circuits)
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9dfe196dc..47dc098a4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -408,7 +408,7 @@ namespace { } if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || - cell->type == "$ge" || cell->type == "$gt") { + cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") { param("\\A_SIGNED"); param("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); |