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| author | N. Engelhardt <nak@symbioticeda.com> | 2020-03-30 13:51:12 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-30 13:51:12 +0200 |
| commit | 2c847e7efec5e940331a94580fad99375ce73c6f (patch) | |
| tree | c87b514d072beb687287ae0432e57964bf0999b9 /kernel/rtlil.cc | |
| parent | 1dbc70172830c57cda22e4bc82d2db57a2067203 (diff) | |
| parent | 044ca9dde409e3c91542fe95513d6641110f8462 (diff) | |
| download | yosys-2c847e7efec5e940331a94580fad99375ce73c6f.tar.gz yosys-2c847e7efec5e940331a94580fad99375ce73c6f.tar.bz2 yosys-2c847e7efec5e940331a94580fad99375ce73c6f.zip | |
Merge pull request #1778 from rswarbrick/sv-defines
Add support for SystemVerilog-style `define to Verilog frontend
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 06181b763..79e50cccd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -21,6 +21,7 @@ #include "kernel/macc.h" #include "kernel/celltypes.h" #include "frontends/verilog/verilog_frontend.h" +#include "frontends/verilog/preproc.h" #include "backends/ilang/ilang_backend.h" #include <string.h> @@ -379,6 +380,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) } RTLIL::Design::Design() + : verilog_defines (new define_map_t) { static unsigned int hashidx_count = 123456789; hashidx_count = mkhash_xorshift(hashidx_count); |