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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
| commit | 1e67099b77904802880ad7c53d2cac33c6df456f (patch) | |
| tree | 87deccc08f9e4bbbc7d2448852daf68d4ba0b35e /kernel/rtlil.cc | |
| parent | 9a1eb45c7517f224a2516ce235fd53d01d9ef908 (diff) | |
| download | yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.gz yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.bz2 yosys-1e67099b77904802880ad7c53d2cac33c6df456f.zip | |
Added $assert cell
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 661525735..7638d4689 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -595,6 +595,13 @@ namespace { return; } + if (cell->type == "$assert") { + port("\\A", 1); + port("\\EN", 1); + check_expected(); + return; + } + if (cell->type == "$_INV_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } if (cell->type == "$_OR_") { check_gate("ABY"); return; } |