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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-31 03:55:13 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-31 03:55:13 +0100 |
| commit | 60f16e17afc81d8bbae722c13ef173329129494a (patch) | |
| tree | b0c2e91f8b1bb8959d9d645a1ee86a13a783f256 /kernel/modtools.h | |
| parent | 6fef4b82a2315830f99eeca3a4e80697a90a8447 (diff) | |
| download | yosys-60f16e17afc81d8bbae722c13ef173329129494a.tar.gz yosys-60f16e17afc81d8bbae722c13ef173329129494a.tar.bz2 yosys-60f16e17afc81d8bbae722c13ef173329129494a.zip | |
hotfix for ModInfo
Diffstat (limited to 'kernel/modtools.h')
| -rw-r--r-- | kernel/modtools.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/modtools.h b/kernel/modtools.h index 558cc08b8..113b0918d 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -70,7 +70,7 @@ struct ModIndex : public RTLIL::Monitor SigMap sigmap; RTLIL::Module *module; - dict<RTLIL::SigBit, SigBitInfo> database; + std::map<RTLIL::SigBit, SigBitInfo> database; bool auto_reload_module; void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig) |