diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-18 11:21:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-18 11:21:53 -0700 |
| commit | 4555b5b81981b74fa20909a72353d45e7be011ad (patch) | |
| tree | 5ca80102e513e17bc8138dbc46062fda7a65e7bb /kernel/modtools.h | |
| parent | 8b12e97153a30cbc78d97a0f9ded26b653097949 (diff) | |
| download | yosys-4555b5b81981b74fa20909a72353d45e7be011ad.tar.gz yosys-4555b5b81981b74fa20909a72353d45e7be011ad.tar.bz2 yosys-4555b5b81981b74fa20909a72353d45e7be011ad.zip | |
kernel: more pass by const ref, more speedups
Diffstat (limited to 'kernel/modtools.h')
| -rw-r--r-- | kernel/modtools.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/modtools.h b/kernel/modtools.h index 409562eb9..715a35c17 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor #endif } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE { log_assert(module == cell->module); |