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authorJannis Harder <me@jix.one>2022-10-21 15:41:20 +0200
committerJannis Harder <me@jix.one>2022-10-24 12:03:01 +0200
commitc77b7343d0412a009436a57764d907e2ae332da2 (patch)
tree3213d3d6940c16b58b369034bfc2cbf875967f10 /kernel/mem.h
parent4f4cff00800dec70796d4d5ec70c73eef837f948 (diff)
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Consistent $mux undef handling
* Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
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