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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-01-27 23:26:56 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-01-28 08:48:33 +0100 |
commit | bac750fb9979e4faa7b2925106b58eeddb570a75 (patch) | |
tree | 918d3e73eb7cd729b04f877d084a5f41f262742a /kernel/mem.h | |
parent | 9a2294f285489950014d5087b7ccad1b4c331474 (diff) | |
download | yosys-bac750fb9979e4faa7b2925106b58eeddb570a75.tar.gz yosys-bac750fb9979e4faa7b2925106b58eeddb570a75.tar.bz2 yosys-bac750fb9979e4faa7b2925106b58eeddb570a75.zip |
kernel/mem: Add read-first semantic emulation code.
Diffstat (limited to 'kernel/mem.h')
-rw-r--r-- | kernel/mem.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/mem.h b/kernel/mem.h index 4d0a1d702..ae87b1285 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -74,6 +74,9 @@ struct MemWr : RTLIL::AttrObject { res[i] = State(sub >> i & 1); return res; } + + std::pair<SigSpec, std::vector<int>> compress_en(); + SigSpec decompress_en(const std::vector<int> &swizzle, SigSpec sig); }; struct MemInit : RTLIL::AttrObject { @@ -209,6 +212,15 @@ struct Mem : RTLIL::AttrObject { // emulation logic. void emulate_rd_srst_over_ce(int idx); + // Returns true iff emulate_read_first makes sense to call. + bool emulate_read_first_ok(); + + // Emulates all read-first read-write port relationships in terms of + // all-transparent ports, by delaying all write ports by one cycle. + // This can only be used when all read ports and all write ports are + // in the same clock domain. + void emulate_read_first(FfInitVals *initvals); + Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {} }; |