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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
| commit | 6872805a3eb738a0a5921b232022abfd507cebb8 (patch) | |
| tree | b871344e8f96cd30c5a6bc3f275476e30f792de0 /kernel/macc.h | |
| parent | 6b51c154c6812f58676402ebbbdbb18d053ca4be (diff) | |
| parent | bb2d5bc4f85ac95104fbd2591ad92ebf0c22e11d (diff) | |
| download | yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.gz yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.bz2 yosys-6872805a3eb738a0a5921b232022abfd507cebb8.zip | |
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Diffstat (limited to 'kernel/macc.h')
| -rw-r--r-- | kernel/macc.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/kernel/macc.h b/kernel/macc.h index e07e7e01a..371f6737d 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -99,10 +99,10 @@ struct Macc void from_cell(RTLIL::Cell *cell) { - RTLIL::SigSpec port_a = cell->getPort(ID(A)); + RTLIL::SigSpec port_a = cell->getPort(ID::A); ports.clear(); - bit_ports = cell->getPort(ID(B)); + bit_ports = cell->getPort(ID::B); std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits; int config_cursor = 0; @@ -191,8 +191,8 @@ struct Macc port_a.append(port.in_b); } - cell->setPort(ID(A), port_a); - cell->setPort(ID(B), bit_ports); + cell->setPort(ID::A, port_a); + cell->setPort(ID::B, bit_ports); cell->setParam(ID(CONFIG), config_bits); cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); cell->setParam(ID(A_WIDTH), GetSize(port_a)); |