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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-18 11:47:46 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-18 11:47:46 +0200 |
commit | 4a32e29445f65edd1726808a7353a9d0e2560c00 (patch) | |
tree | 179544dd193fe72b3658269cb22a6eae66bee8a1 /kernel/macc.h | |
parent | 5f561bdcb1d562d6f975b4a27beca1b8b7af908f (diff) | |
parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
download | yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.tar.gz yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.tar.bz2 yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.zip |
Merge remote-tracking branch 'upstream/master' into anlogic_fixes
Diffstat (limited to 'kernel/macc.h')
-rw-r--r-- | kernel/macc.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/kernel/macc.h b/kernel/macc.h index c7595ebc1..371f6737d 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -99,16 +99,16 @@ struct Macc void from_cell(RTLIL::Cell *cell) { - RTLIL::SigSpec port_a = cell->getPort("\\A"); + RTLIL::SigSpec port_a = cell->getPort(ID::A); ports.clear(); - bit_ports = cell->getPort("\\B"); + bit_ports = cell->getPort(ID::B); - std::vector<RTLIL::State> config_bits = cell->getParam("\\CONFIG").bits; + std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits; int config_cursor = 0; #ifndef NDEBUG - int config_width = cell->getParam("\\CONFIG_WIDTH").as_int(); + int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int(); log_assert(GetSize(config_bits) >= config_width); #endif @@ -191,12 +191,12 @@ struct Macc port_a.append(port.in_b); } - cell->setPort("\\A", port_a); - cell->setPort("\\B", bit_ports); - cell->setParam("\\CONFIG", config_bits); - cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits)); - cell->setParam("\\A_WIDTH", GetSize(port_a)); - cell->setParam("\\B_WIDTH", GetSize(bit_ports)); + cell->setPort(ID::A, port_a); + cell->setPort(ID::B, bit_ports); + cell->setParam(ID(CONFIG), config_bits); + cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); + cell->setParam(ID(A_WIDTH), GetSize(port_a)); + cell->setParam(ID(B_WIDTH), GetSize(bit_ports)); } bool eval(RTLIL::Const &result) const |