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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 10:07:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 10:07:27 -0700 |
| commit | 2f4e0a5388c58726ec8b3d073e3ebc51897fd13c (patch) | |
| tree | bb5f6bb14eb4bd83a7e302b7e4666c716234beee /kernel/macc.h | |
| parent | e301440a0bae76dcff159c77274c91aad40021c0 (diff) | |
| parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
| download | yosys-2f4e0a5388c58726ec8b3d073e3ebc51897fd13c.tar.gz yosys-2f4e0a5388c58726ec8b3d073e3ebc51897fd13c.tar.bz2 yosys-2f4e0a5388c58726ec8b3d073e3ebc51897fd13c.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'kernel/macc.h')
| -rw-r--r-- | kernel/macc.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/kernel/macc.h b/kernel/macc.h index e07e7e01a..371f6737d 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -99,10 +99,10 @@ struct Macc void from_cell(RTLIL::Cell *cell) { - RTLIL::SigSpec port_a = cell->getPort(ID(A)); + RTLIL::SigSpec port_a = cell->getPort(ID::A); ports.clear(); - bit_ports = cell->getPort(ID(B)); + bit_ports = cell->getPort(ID::B); std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits; int config_cursor = 0; @@ -191,8 +191,8 @@ struct Macc port_a.append(port.in_b); } - cell->setPort(ID(A), port_a); - cell->setPort(ID(B), bit_ports); + cell->setPort(ID::A, port_a); + cell->setPort(ID::B, bit_ports); cell->setParam(ID(CONFIG), config_bits); cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); cell->setParam(ID(A_WIDTH), GetSize(port_a)); |