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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-10 09:52:14 +0200 | 
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-10 09:52:14 +0200 | 
| commit | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (patch) | |
| tree | 21d24c49c50f17a53a9bc8fe4118752ff845e55d /kernel/celltypes.h | |
| parent | 4f812131653ebea06e3d1c3e7599492992edb771 (diff) | |
| parent | 6d77236f3845cd8785e7bdd4da3c5ef966be6043 (diff) | |
| download | yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.gz yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.tar.bz2 yosys-f54bf1631ff37a83733c162e6ebd188c1d5ea18f.zip  | |
Merge pull request #1258 from YosysHQ/eddie/cleanup
Cleanup a few barnacles across codebase
Diffstat (limited to 'kernel/celltypes.h')
| -rw-r--r-- | kernel/celltypes.h | 12 | 
1 files changed, 6 insertions, 6 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index d1d9bf943..1256fbcba 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -282,8 +282,8 @@ struct CellTypes  	static RTLIL::Const eval_not(RTLIL::Const v)  	{  		for (auto &bit : v.bits) -			if (bit == RTLIL::S0) bit = RTLIL::S1; -			else if (bit == RTLIL::S1) bit = RTLIL::S0; +			if (bit == State::S0) bit = State::S1; +			else if (bit == State::S1) bit = State::S0;  		return v;  	} @@ -389,15 +389,15 @@ struct CellTypes  			std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;  			while (GetSize(t) < (1 << width)) -				t.push_back(RTLIL::S0); +				t.push_back(State::S0);  			t.resize(1 << width);  			for (int i = width-1; i >= 0; i--) {  				RTLIL::State sel = arg1.bits.at(i);  				std::vector<RTLIL::State> new_t; -				if (sel == RTLIL::S0) +				if (sel == State::S0)  					new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2); -				else if (sel == RTLIL::S1) +				else if (sel == State::S1)  					new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());  				else  					for (int j = 0; j < GetSize(t)/2; j++) @@ -416,7 +416,7 @@ struct CellTypes  			std::vector<RTLIL::State> t = cell->parameters.at("\\TABLE").bits;  			while (GetSize(t) < width*depth*2) -				t.push_back(RTLIL::S0); +				t.push_back(State::S0);  			RTLIL::State default_ret = State::S0;  | 
