Merge remote-tracking branch 'upstream/master'

# Conflicts:
#	CHANGELOG
#	frontends/verific/verific.cc
#	frontends/verilog/verilog_parser.y

1 files changed, 12 insertions, 7 deletions

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 6041168bb..8b8a56111 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -257,7 +257,7 @@ struct CellTypes
 		return v;
 	}
 
-	static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
+	static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
 	{
 		if (type == "$sshr" && !signed1)
 			type = "$shr";
@@ -329,10 +329,15 @@ struct CellTypes
 		if (type == "$_ORNOT_")
 			return const_or(arg1, eval_not(arg2), false, false, 1);
 
+		if (errp != nullptr) {
+			*errp = true;
+			return State::Sm;
+		}
+
 		log_abort();
 	}
 
-	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2)
+	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
 	{
 		if (cell->type == "$slice") {
 			RTLIL::Const ret;
@@ -415,10 +420,10 @@ struct CellTypes
 		bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
 		bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
 		int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
-		return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
+		return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
 	}
 
-	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3)
+	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
 	{
 		if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
 			RTLIL::Const ret = arg1;
@@ -436,10 +441,10 @@ struct CellTypes
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
 
 		log_assert(arg3.bits.size() == 0);
-		return eval(cell, arg1, arg2);
+		return eval(cell, arg1, arg2, errp);
 	}
 
-	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4)
+	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
 	{
 		if (cell->type == "$_AOI4_")
 			return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
@@ -447,7 +452,7 @@ struct CellTypes
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
 
 		log_assert(arg4.bits.size() == 0);
-		return eval(cell, arg1, arg2, arg3);
+		return eval(cell, arg1, arg2, arg3, errp);
 	}
 };