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author | Xiretza <xiretza@xiretza.xyz> | 2020-04-21 12:51:58 +0200 |
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committer | Xiretza <xiretza@xiretza.xyz> | 2020-05-28 22:59:04 +0200 |
commit | edd8ff2c0778d97808869488cc7394151456c4ca (patch) | |
tree | 797418b87588ae7a69992b7f107dfd5cdfdec08d /kernel/celltypes.h | |
parent | 17163cf43a6b6eec9aac44f6a4463dda54b8ed68 (diff) | |
download | yosys-edd8ff2c0778d97808869488cc7394151456c4ca.tar.gz yosys-edd8ff2c0778d97808869488cc7394151456c4ca.tar.bz2 yosys-edd8ff2c0778d97808869488cc7394151456c4ca.zip |
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
Diffstat (limited to 'kernel/celltypes.h')
-rw-r--r-- | kernel/celltypes.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 37c251f7e..db54436cb 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -114,7 +114,7 @@ struct CellTypes ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), - ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($modfloor), ID($pow), + ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($logic_and), ID($logic_or), ID($concat), ID($macc) }; @@ -304,6 +304,7 @@ struct CellTypes HANDLE_CELL_TYPE(mul) HANDLE_CELL_TYPE(div) HANDLE_CELL_TYPE(mod) + HANDLE_CELL_TYPE(divfloor) HANDLE_CELL_TYPE(modfloor) HANDLE_CELL_TYPE(pow) HANDLE_CELL_TYPE(pos) |