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author | Clifford Wolf <clifford@clifford.at> | 2014-08-31 17:42:38 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-08-31 17:43:31 +0200 |
commit | a1c7d4a8e24c14eae7f1f7e383f18b25a190875b (patch) | |
tree | 4206154a12fe9f1b8740d359256895f70c0e3d39 /kernel/celltypes.h | |
parent | 0b6769af3f7578dfb31c801014413174bd230208 (diff) | |
download | yosys-a1c7d4a8e24c14eae7f1f7e383f18b25a190875b.tar.gz yosys-a1c7d4a8e24c14eae7f1f7e383f18b25a190875b.tar.bz2 yosys-a1c7d4a8e24c14eae7f1f7e383f18b25a190875b.zip |
Added eval model for $lut cells
Diffstat (limited to 'kernel/celltypes.h')
-rw-r--r-- | kernel/celltypes.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index c1bb1d036..4a8be04d3 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -297,6 +297,32 @@ struct CellTypes return ret; } + if (cell->type == "$lut") + { + int width = cell->parameters.at("\\WIDTH").as_int(); + + std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits; + while (SIZE(t) < (1 << width)) + t.push_back(RTLIL::S0); + t.resize(1 << width); + + for (int i = width-1; i >= 0; i--) { + RTLIL::State sel = arg1.bits.at(i); + std::vector<RTLIL::State> new_t; + if (sel == RTLIL::S0) + new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + SIZE(t)/2); + else if (sel == RTLIL::S1) + new_t = std::vector<RTLIL::State>(t.begin() + SIZE(t)/2, t.end()); + else + for (int j = 0; j < SIZE(t)/2; j++) + new_t.push_back(t[j] == t[j + SIZE(t)/2] ? t[j] : RTLIL::Sx); + t.swap(new_t); + } + + log_assert(SIZE(t) == 1); + return t; + } + bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool(); int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1; |