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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-28 19:24:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-28 19:24:24 +0100 |
| commit | 137f35373f4ef0d1ddf212187e537e48d077b1f4 (patch) | |
| tree | a77df3913cb442b444f530648b71d4777e0921d2 /kernel/celltypes.h | |
| parent | f3a97b75c78bd6f3670445129405213c0a015481 (diff) | |
| download | yosys-137f35373f4ef0d1ddf212187e537e48d077b1f4.tar.gz yosys-137f35373f4ef0d1ddf212187e537e48d077b1f4.tar.bz2 yosys-137f35373f4ef0d1ddf212187e537e48d077b1f4.zip | |
Changed more code to dict<> and pool<>
Diffstat (limited to 'kernel/celltypes.h')
| -rw-r--r-- | kernel/celltypes.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 5ba4dd88b..32e144194 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -27,13 +27,13 @@ YOSYS_NAMESPACE_BEGIN struct CellType { RTLIL::IdString type; - std::set<RTLIL::IdString> inputs, outputs; + pool<RTLIL::IdString> inputs, outputs; bool is_evaluable; }; struct CellTypes { - std::map<RTLIL::IdString, CellType> cell_types; + dict<RTLIL::IdString, CellType> cell_types; CellTypes() { @@ -55,7 +55,7 @@ struct CellTypes setup_stdcells_mem(); } - void setup_type(RTLIL::IdString type, const std::set<RTLIL::IdString> &inputs, const std::set<RTLIL::IdString> &outputs, bool is_evaluable = false) + void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false) { CellType ct = {type, inputs, outputs, is_evaluable}; cell_types[ct.type] = ct; @@ -63,7 +63,7 @@ struct CellTypes void setup_module(RTLIL::Module *module) { - std::set<RTLIL::IdString> inputs, outputs; + pool<RTLIL::IdString> inputs, outputs; for (RTLIL::IdString wire_name : module->ports) { RTLIL::Wire *wire = module->wire(wire_name); if (wire->port_input) @@ -109,7 +109,7 @@ struct CellTypes setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true); setup_type("$fa", {"\\A", "\\B", "\\C"}, {"\\X", "\\Y"}, true); - setup_type("$assert", {"\\A", "\\EN"}, std::set<RTLIL::IdString>(), true); + setup_type("$assert", {"\\A", "\\EN"}, pool<RTLIL::IdString>(), true); } void setup_internals_mem() @@ -123,7 +123,7 @@ struct CellTypes setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"}); setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"}); - setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, std::set<RTLIL::IdString>()); + setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, pool<RTLIL::IdString>()); setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"}); setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"}); |