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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:39:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-25 16:39:25 +0200 |
| commit | 8537c4d2061db1ee11defc357781c6c534be5b3d (patch) | |
| tree | 4fe2f7e4f7082ee6add823da39910912a52dc6e1 /kernel/celledges.cc | |
| parent | 5b944ef11b8964a00d833ad29c96ad46da06f7a3 (diff) | |
| download | yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.tar.gz yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.tar.bz2 yosys-8537c4d2061db1ee11defc357781c6c534be5b3d.zip | |
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
Diffstat (limited to 'kernel/celledges.cc')
| -rw-r--r-- | kernel/celledges.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 430425ea8..556e8b826 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -158,7 +158,7 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) PRIVATE_NAMESPACE_END -bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell) +bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell) { if (cell->type.in("$not", "$pos")) { bitwise_unary_op(this, cell); |