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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 10:07:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 10:07:27 -0700 |
| commit | 2f4e0a5388c58726ec8b3d073e3ebc51897fd13c (patch) | |
| tree | bb5f6bb14eb4bd83a7e302b7e4666c716234beee /kernel/celledges.cc | |
| parent | e301440a0bae76dcff159c77274c91aad40021c0 (diff) | |
| parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
| download | yosys-2f4e0a5388c58726ec8b3d073e3ebc51897fd13c.tar.gz yosys-2f4e0a5388c58726ec8b3d073e3ebc51897fd13c.tar.bz2 yosys-2f4e0a5388c58726ec8b3d073e3ebc51897fd13c.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'kernel/celledges.cc')
| -rw-r--r-- | kernel/celledges.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 7a324a06e..d0bb99e83 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -41,7 +41,7 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -71,7 +71,7 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -87,7 +87,7 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -114,7 +114,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; int a_width = GetSize(cell->getPort(A)); @@ -124,7 +124,7 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); @@ -138,7 +138,7 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y); + IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); |