Removed $bu0 cell type

1 files changed, 0 insertions, 21 deletions

diff --git a/kernel/calc.cc b/kernel/calc.cc
index da03f6164..41179d045 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -26,19 +26,6 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-static void extend(RTLIL::Const &arg, int width, bool is_signed)
-{
-	RTLIL::State padding = RTLIL::State::S0;
-
-	if (arg.bits.size() > 0 && (is_signed || arg.bits.back() > RTLIL::State::S1))
-		padding = arg.bits.back();
-
-	while (int(arg.bits.size()) < width)
-		arg.bits.push_back(padding);
-
-	arg.bits.resize(width);
-}
-
 static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
 {
 	RTLIL::State padding = RTLIL::State::S0;
@@ -580,14 +567,6 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo
 	return arg1_ext;
 }
 
-RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
-{
-	RTLIL::Const arg1_ext = arg1;
-	extend_u0(arg1_ext, result_len, signed1);
-
-	return arg1_ext;
-}
-
 RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
 {
 	RTLIL::Const arg1_ext = arg1;