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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 17:15:01 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 17:15:01 +0200 |
| commit | b17d6531c833f9064c5888c694aa24e8a395b72a (patch) | |
| tree | f1cd2bd0044f938cd9371a63b5650df0e0fc20a7 /frontends/vhdl2verilog | |
| parent | 2f54345cff3aea768bb89754654127a3b0ee58e9 (diff) | |
| download | yosys-b17d6531c833f9064c5888c694aa24e8a395b72a.tar.gz yosys-b17d6531c833f9064c5888c694aa24e8a395b72a.tar.bz2 yosys-b17d6531c833f9064c5888c694aa24e8a395b72a.zip | |
Added "make PRETTY=1"
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions