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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-09 17:07:20 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-09 17:07:20 +0200 |
| commit | 9d4362990f514ffd2aad3170ec7382f21b8bca67 (patch) | |
| tree | 3aab1691828e3ab37403e4a66f379696dc66df7e /frontends/vhdl2verilog | |
| parent | b9811d5aff7ca31daa214386a041af0865813813 (diff) | |
| download | yosys-9d4362990f514ffd2aad3170ec7382f21b8bca67.tar.gz yosys-9d4362990f514ffd2aad3170ec7382f21b8bca67.tar.bz2 yosys-9d4362990f514ffd2aad3170ec7382f21b8bca67.zip | |
Fixed "share" for complex scenarios with never-active cells
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions