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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-16 11:38:02 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-16 11:38:02 +0200 |
| commit | 73e0e13d2f1b959a05d69ed715c8fdde84894d6f (patch) | |
| tree | 8a604b9990ca8e3ffd405b5e74a2d0e01141fb4b /frontends/vhdl2verilog | |
| parent | 964a67ac4194bb85fb3cb7a90a62dc1e4a685ea4 (diff) | |
| download | yosys-73e0e13d2f1b959a05d69ed715c8fdde84894d6f.tar.gz yosys-73e0e13d2f1b959a05d69ed715c8fdde84894d6f.tar.bz2 yosys-73e0e13d2f1b959a05d69ed715c8fdde84894d6f.zip | |
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions