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| author | Aleks-Daniel Jakimenko-Aleksejev <alex.jakimenko@gmail.com> | 2016-11-19 20:51:50 +0200 |
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| committer | Aleks-Daniel Jakimenko-Aleksejev <alex.jakimenko@gmail.com> | 2016-11-19 20:51:50 +0200 |
| commit | 3c86da8000e0064a36b24d7829d83bca1d09c5fc (patch) | |
| tree | 3e46009356f19af5b46c0a4ee587acdea3b735ad /frontends/vhdl2verilog | |
| parent | 751ad3c6180ad5180a163e263dfcdebc38683a1b (diff) | |
| download | yosys-3c86da8000e0064a36b24d7829d83bca1d09c5fc.tar.gz yosys-3c86da8000e0064a36b24d7829d83bca1d09c5fc.tar.bz2 yosys-3c86da8000e0064a36b24d7829d83bca1d09c5fc.zip | |
Keep lines under 80 characters
Recent README changes added some characters to existing lines, which
made them longer than 80 characters. This commit fixes that.
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions