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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-20 23:30:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-20 23:30:15 +0100 |
| commit | 236fc4209c17bf96b37e6f8a29a8aa3f24d5df45 (patch) | |
| tree | 3dcf839a2dbe77f0ab8a7f447a8e44c2f8ef9c67 /frontends/vhdl2verilog/vhdl2verilog.cc | |
| parent | 483c99fe46d6b1cd35abddd38a629d30e13289b4 (diff) | |
| download | yosys-236fc4209c17bf96b37e6f8a29a8aa3f24d5df45.tar.gz yosys-236fc4209c17bf96b37e6f8a29a8aa3f24d5df45.tar.bz2 yosys-236fc4209c17bf96b37e6f8a29a8aa3f24d5df45.zip | |
Added "extract -map %<design_name>"
Diffstat (limited to 'frontends/vhdl2verilog/vhdl2verilog.cc')
0 files changed, 0 insertions, 0 deletions