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| author | Xiretza <xiretza@xiretza.xyz> | 2020-04-21 12:51:58 +0200 |
|---|---|---|
| committer | Xiretza <xiretza@xiretza.xyz> | 2020-05-28 22:59:04 +0200 |
| commit | edd8ff2c0778d97808869488cc7394151456c4ca (patch) | |
| tree | 797418b87588ae7a69992b7f107dfd5cdfdec08d /frontends/verilog | |
| parent | 17163cf43a6b6eec9aac44f6a4463dda54b8ed68 (diff) | |
| download | yosys-edd8ff2c0778d97808869488cc7394151456c4ca.tar.gz yosys-edd8ff2c0778d97808869488cc7394151456c4ca.tar.bz2 yosys-edd8ff2c0778d97808869488cc7394151456c4ca.zip | |
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions