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| author | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-10 20:23:55 +0100 |
|---|---|---|
| committer | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-10 20:23:55 +0100 |
| commit | d091be401140088431ac2c1bf2bc97415e37c9ff (patch) | |
| tree | 87868be85a3b694f76782703322482d7c97b151d /frontends/verilog | |
| parent | 113f129b348c48fff67242fe65906b3821ae7bd4 (diff) | |
| download | yosys-d091be401140088431ac2c1bf2bc97415e37c9ff.tar.gz yosys-d091be401140088431ac2c1bf2bc97415e37c9ff.tar.bz2 yosys-d091be401140088431ac2c1bf2bc97415e37c9ff.zip | |
- libs/ezsat/ezminisat.cc: use sigemptyset() to clear sig_action.sa_mask; use SA_RESTART flag for improved robustness of code that is not signal-aware.
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions