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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-06 12:34:05 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-06 12:34:05 +0200 |
| commit | b894187cf66dfa346eddeccf42c38c0635db9524 (patch) | |
| tree | 7a670a3409ff61309f5050adb3042f662be6ce8c /frontends/verilog | |
| parent | 30cedaca10ef822fcc97f2d892186ad8bd9159cd (diff) | |
| parent | 03e0d3a17cf27858d16e0169614b6575c7dac538 (diff) | |
| download | yosys-b894187cf66dfa346eddeccf42c38c0635db9524.tar.gz yosys-b894187cf66dfa346eddeccf42c38c0635db9524.tar.bz2 yosys-b894187cf66dfa346eddeccf42c38c0635db9524.zip | |
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
Added support for parsing attributes on port connections.
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8244a8f44..ccdab987f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1532,27 +1532,31 @@ cell_port_list_rules: cell_port | cell_port_list_rules ',' cell_port; cell_port: - /* empty */ { + attr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); + free_attr($1); } | - expr { + attr expr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); - node->children.push_back($1); + node->children.push_back($2); + free_attr($1); } | - '.' TOK_ID '(' expr ')' { + attr '.' TOK_ID '(' expr ')' { AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; + node->str = *$3; astbuf2->children.push_back(node); - node->children.push_back($4); - delete $2; + node->children.push_back($5); + delete $3; + free_attr($1); } | - '.' TOK_ID '(' ')' { + attr '.' TOK_ID '(' ')' { AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; + node->str = *$3; astbuf2->children.push_back(node); - delete $2; + delete $3; + free_attr($1); }; always_stmt: |