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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-06 12:10:28 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-06 12:10:28 -0700 |
| commit | a299e606f864942c7edf90c4ad3998f4f4a346cf (patch) | |
| tree | 2150af3a69a0bb174f0a53139e606b5d3ed7b803 /frontends/verilog | |
| parent | 283b1130a651324ff870059dc3b1cf869948db93 (diff) | |
| parent | 8f9bba1bbfdb56630dadd75a3f92f7bfb26b3df6 (diff) | |
| download | yosys-a299e606f864942c7edf90c4ad3998f4f4a346cf.tar.gz yosys-a299e606f864942c7edf90c4ad3998f4f4a346cf.tar.bz2 yosys-a299e606f864942c7edf90c4ad3998f4f4a346cf.zip | |
Merge pull request #2028 from zachjs/master
verilog: allow null gen-if then block
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 5d6e43330..4a531c09f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2537,7 +2537,12 @@ gen_stmt: ast_stack.back()->children.push_back(node); ast_stack.push_back(node); ast_stack.back()->children.push_back($3); - } gen_stmt_block opt_gen_else { + AstNode *block = new AstNode(AST_GENBLOCK); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + } gen_stmt_or_null { + ast_stack.pop_back(); + } opt_gen_else { SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); } | |