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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-01 15:25:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-01 15:25:42 +0200 |
| commit | 97a17d39e2f0088e02ed8496d905528722115674 (patch) | |
| tree | 8929691e146e0ab75829ef50e1d585861a06db06 /frontends/verilog | |
| parent | 5e641acc905a5c99d037378f6b7a481c43eb7de0 (diff) | |
| download | yosys-97a17d39e2f0088e02ed8496d905528722115674.tar.gz yosys-97a17d39e2f0088e02ed8496d905528722115674.tar.bz2 yosys-97a17d39e2f0088e02ed8496d905528722115674.zip | |
Packed SigBit::data and SigBit::offset in a union
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions