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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-30 15:19:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-30 15:19:10 +0200 |
| commit | 9268cd16135db87920ee49a54a16dab62fc1f4a8 (patch) | |
| tree | 318cc988782f61ce05d132c5db8332d0fb64797d /frontends/verilog | |
| parent | 314ff1e4ca00ef8024bbb0d2f031efd78b01f9a1 (diff) | |
| download | yosys-9268cd16135db87920ee49a54a16dab62fc1f4a8.tar.gz yosys-9268cd16135db87920ee49a54a16dab62fc1f4a8.tar.bz2 yosys-9268cd16135db87920ee49a54a16dab62fc1f4a8.zip | |
Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions