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| author | Clifford Wolf <clifford@clifford.at> | 2017-06-07 12:30:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-06-07 12:30:24 +0200 |
| commit | 8f8baccfde62d238025024eb1060ae0aba4c77e3 (patch) | |
| tree | 302be16a368f4df3b010f0ad6d2edf4135ad5a1e /frontends/verilog | |
| parent | 129984e115d318e00ec065ea76cb8c5926393bc4 (diff) | |
| download | yosys-8f8baccfde62d238025024eb1060ae0aba4c77e3.tar.gz yosys-8f8baccfde62d238025024eb1060ae0aba4c77e3.tar.bz2 yosys-8f8baccfde62d238025024eb1060ae0aba4c77e3.zip | |
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 154b59ebc..c5ff3d402 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -764,6 +764,7 @@ wire_name_and_opt_assign: AstNode *fcall = new AstNode(AST_FCALL); wire->str = ast_stack.back()->children.back()->str; fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq"; + fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall)); } } | |