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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:13 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:38 +0200 |
| commit | 7bffde6abdaf6fc2ed090946442f90b2438e6126 (patch) | |
| tree | 24091283baf740e0ffd5b347da84771ed28791a7 /frontends/verilog | |
| parent | 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (diff) | |
| download | yosys-7bffde6abdaf6fc2ed090946442f90b2438e6126.tar.gz yosys-7bffde6abdaf6fc2ed090946442f90b2438e6126.tar.bz2 yosys-7bffde6abdaf6fc2ed090946442f90b2438e6126.zip | |
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions