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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 13:01:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 13:01:17 -0700 |
| commit | 437fec0d88b4a2ad172edf0d1a861a38845f3b1d (patch) | |
| tree | f8cc931e846d3080768bd8e3b1141d955491c06e /frontends/verilog | |
| parent | fd89c1056ef8a8010c77a5b645df14908e3c68d9 (diff) | |
| download | yosys-437fec0d88b4a2ad172edf0d1a861a38845f3b1d.tar.gz yosys-437fec0d88b4a2ad172edf0d1a861a38845f3b1d.tar.bz2 yosys-437fec0d88b4a2ad172edf0d1a861a38845f3b1d.zip | |
Map to SB_LUT4 from fastest input first
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions