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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
| commit | 295e352ba6aa1bd71431abc21a8f93735968cae6 (patch) | |
| tree | 2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /frontends/verilog | |
| parent | c854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff) | |
| download | yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.tar.gz yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.tar.bz2 yosys-295e352ba6aa1bd71431abc21a8f93735968cae6.zip | |
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 1d26de73f..1ef2f6608 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -90,7 +90,7 @@ struct VerilogFrontend : public Frontend { log(" do not run the pre-processor\n"); log("\n"); log(" -lib\n"); - log(" only create empty placeholder modules\n"); + log(" only create empty blackbox modules\n"); log("\n"); log(" -noopt\n"); log(" don't perform basic optimizations (such as const folding) in the\n"); |