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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-06-16 06:04:04 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-06-16 08:14:08 +0200 |
| commit | 25a4cd7020c100838e359b393ffb545532e69101 (patch) | |
| tree | 7144e7bc8eaef07857ae85b5f1e6684b4e79f536 /frontends/verilog | |
| parent | 3046a06490831b171a04b000f3676c5df0af68d5 (diff) | |
| download | yosys-25a4cd7020c100838e359b393ffb545532e69101.tar.gz yosys-25a4cd7020c100838e359b393ffb545532e69101.tar.bz2 yosys-25a4cd7020c100838e359b393ffb545532e69101.zip | |
memory_libmap: Fix params emitted for unused ports for consistency.
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions