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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-15 09:52:01 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-15 09:52:01 +0100 |
| commit | 1d82a88e948e614ada66b0fd59e9cc0aa569afae (patch) | |
| tree | 4626094558bb891f4c9c33330549df3609e38a0e /frontends/verilog | |
| parent | 0994cfce7b15bbbea28a09e141a669c7228b6a89 (diff) | |
| parent | fc2dd7ec8e433bf54fffdb85e9aa2556fe3e39a2 (diff) | |
| download | yosys-1d82a88e948e614ada66b0fd59e9cc0aa569afae.tar.gz yosys-1d82a88e948e614ada66b0fd59e9cc0aa569afae.tar.bz2 yosys-1d82a88e948e614ada66b0fd59e9cc0aa569afae.zip | |
Merge pull request #788 from whitequark/master
Document $tribuf and some gates
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