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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 16:19:23 -0700 |
| commit | 0f094fba08b69baa2329e749daf19f41a624a0a0 (patch) | |
| tree | 351b06434e43232ac9c8f893f4528137f298fa70 /frontends/verilog | |
| parent | 36a219063ad7b4e70581bf83a00365db764737bf (diff) | |
| download | yosys-0f094fba08b69baa2329e749daf19f41a624a0a0.tar.gz yosys-0f094fba08b69baa2329e749daf19f41a624a0a0.tar.bz2 yosys-0f094fba08b69baa2329e749daf19f41a624a0a0.zip | |
Pad all boxes so that all input/output connections specified
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions